摘要
研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。
The linear drain current degradation of n MOSFETs with different channel lengths and gate oxide thickness is investigated at VG=Vn/2 stress mode with forward substrate biases. The forward substrate bias shows stronger dependence on linear drain current degradation of the devices with 0. 135 μm channel length and 2.5 t^m gate oxide thickness than that of devices with 0. 25 μm channel length and 5 μm gate oxide thickness. It is demonstrated that as channel shortens and gate oxide thins,the threshold voltage decrease and parasitic NPN bipolar transistor effect caused by forward substrate bias,as well as the interface traps formed from breaking weak bonds at Si-SiO2 interface by the energetic photons, which are created by channel hot electrons recobination with holes from impact ionization and electrons tunneling gate oxide, degrade linear drain current badly.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2006年第1期20-24,48,共6页
Research & Progress of SSE
基金
国家基础研究项目(G2000036503)资助