基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

5Gb/s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。

A 5 Gb/s monolithic phase-locked clock recovery circuit is designed and realized in a 0.18μm CMOS technology. A half rate bang-bang phase detector and a four-phase ring current-controlled oscillator incorporated with a charge-pump build up half-rate phase-locked loop （PLL） architecture. The measured rms jitter of recovered clock signal is 4.7 ps under the stimulation of a 211-1 bit-long pseudorandom bit sequence at the bit rate of 5 Gb/s. The phase noise is -112.3 dBc/Hz at the 6 MHz offset. The chip area is only 0. 6 mm×0.6 mm and the DC power consumption is less than 90 mW under a single 1.8 V supply.