基于SoC平台的H.264解码器IP核设计

A H.264 decoder IP core based on SoC Platform

介绍了SoC的发展概况和趋势,提出了一种基于SoC平台的H.264解码器优化设计架构。在设计中采取了灵活的帧场自适应解码策略,对于总线时序需求较高的模块采用了流水线设计,对总线进行了时分复用;在可变长解码部分,对各个功能模块进行了控制分离,这些优化除了可有效地减小时钟频率需求外,还可在一定程度上兼容其它的视频压缩标准,如MPEG-2。最后实现了这个设计,并给出了实验结果。

This paper introduces the trend and general situation of SoC. We introduce an optimized and very practical H.26d- decoder architecture too, which is based on a SoC platform. We use flexible Frame/Field adaptive decoding strategy. For those modules which require high bus cycle performance,pipeline design is used to perform the time division multiplexing of the bus;When processing CAVLC, we separate the control of every function unit from each other, those optimization can effectively reduce the clock frequency. This architecture is also compatible with some other video compression standards such as MPEG-2 to some degree. Finally, we implement this design and experimental results are given.