基于Verilog HDL设计的多功能数字钟

Design of Multifunctional Digital Clock Based on Verilog HDL

本文利用VerilogHDL语言自顶向下的设计方法设计多功能数字钟,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过AlteraQuartusⅡ4.1和ModelSimSE6.0完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的数字钟显示中。

In this paper, the process of designing muhifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera Quartus Ⅱ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip.