摘要
自检测电路设计方法有多种多样,本文中介绍了TSC电路的概念,并采用1/3码的动态CMOS设计TSC电路,通过在Cadence环境下仿真,仿真结果表明本设计可行。
In the area of self-checking circuit design, it' s known there are so many techniques. This paper introduces the concept of totally self-checking checker. This paper persents an 1-out-of-3 dynamic CMOS totally self-checking (TSC) checker . Through the emulator of Cadence, the result of experimentation indicates the design is feasible.
出处
《微计算机信息》
北大核心
2006年第04Z期212-213,287,共3页
Control & Automation
基金
受到上海市教委青年基金项目"turbo编码器IP核设计"资助
编号:03AQ85.