一种精确的锁相环IP模块行为级建模

Accurate IP Behavioral Modeling of Phase Lock Loop

根据模拟硬件描述语言Verilog-A的特点,抽取欲设计锁相环各模块的关键参数并加入到利用Vegilog-A建立的相应模块的行为级模型中,并且根据晶体管级仿真结果对行为级模型中的参数进行实时修正,建立了比较精确的中心频率为100MHz的PLL行为级模型。

Based on the characters of the analog hardware description language Verilog-A, embed the parameters extracted from PLL＇s modules into the behavorial_modeling based on the Verilog-A, and according to the simulation-result of transistor-level circuit, the parameters were modified realtime. At last, a accurate behavioral-modeling of one PLL with 100MHz center frequency was founded.