期刊文献+

提高E^2PROM中NMOS管源漏穿通电压的实验研究

An Experimental Study on the Improvement of the Source Drain Punch through Voltage of NMOS Transistor in E 2PROMs
下载PDF
导出
摘要 为了提高E2PROM中N管源漏穿通电压(VPT),用实验的方法对制造工艺进行了研究。结果表明,高能量注入是提高VPT的有效手段,但受到pn结击穿的限制,只适用于低压区短沟N管;DDD工艺可大幅度提高VPT,但pn结击穿电压低于20V,不能应用于高压MOS管; To improve the S D punch through voltage ( V PT )of NMOS transistor in E 2PROMs,an experiment was conducted to demonstrate three different process schemes.It has been shown that 1)high energy implantation is an efficient means to improve V PT ,but it is only suitable for short channel transistor working at low voltage due to the limitation of the p n junction breakdown,2)the double diffusion drain(DDD) technique can greatly increase V PT ,but the low p n junction breakdown voltage (<20 V) prevents it from being used for high voltage MOS transistors,and 3) the most desirable method is a moderate anti punch through implantation plus properly increased channel length for MOS transistors operating at high voltage.
出处 《微电子学》 CAS CSCD 1996年第5期339-341,共3页 Microelectronics
关键词 数字集成电路 存储器 E^2PROM Digital IC,Memory,E 2PROM,Semiconductor process
  • 相关文献

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部