基于流水线的自检测进位相关和加法器设计

A Pipelined Carry-dependent Sum Adder with its Self-checking Structure

文章提出了一种基于流水线设计的具有自检测功能的进位相关和加法器。该加法器包括四个8位进位相关和加法器(CDSA),一个4位超前进位单元(BLCU)和一个奇偶校验器。与普通的行波进位加法器相比,文章设计的加法器硬件实现面积仅增加3.85%,而在关键路径的延时上,该加法器要减少39.2%。

In this paper a pipelined carry-dependent sum adder with the self-checking structure is proposed. The adder includes four 8bits carry-dependent sum adder （CDSA）, a 4bits block carry look-ahead unit （BCLU） and a parity checker. The necessary area of the proposed adder is only about 3.85% over the traditional ripple carry adders, while the sum of the traditional adders is delayed by 39.2% with respect to the proposed adder for 32bits implementation.