H.264/AVC中去块效应环路滤波的VLSI实现

An Implemented VLSI Architecture of Deblocking Filter in H.264/AVC

提出了一种适用于H.264编解码环内去块效应滤波的VLSI结构。利用相邻4×4像素块间数据的依赖关系合理组织数据存储顺序,并通过增加本地SRAM,使垂直滤波数据来自本地,读写外部SDRAM的次数减半,从而大大减少滤波处理的周期数。设置转置寄存器,水平滤波和垂直滤波可共用一维滤波电路。仿真结果显示,一个宏块去块效应滤波仅需要230个周期。在0.18μm工艺下,最大频率100M时,综合逻辑门数为14K。

This paper presents an implemented VLSI architecture for adaptive deblocking loop filter in H.264/AVC. In this architecture, data access is carefully organized and some other measure are adopted, which increase the efficiency of getting data from the local SRAM and highly reduce the total cycles of filtering process. This design supports both horizontal filtering and vertical filtering on the same circuit. Simulation show that only 230 clock cycles are needed to finish filtering a macroblock for dehlocking filter, and the synthesized logic gate count is only 14K under 0.18 μm technology when the maximum frequency is 100MHz.