RS连续编码器的FPGA设计与实现

Design and Implementation of Continuous Reed-Solomon Encoder on FPGA

介绍了Virtex-Ⅱ系列FPGA(现场可编程门阵列)的时钟管理模块DCM(数字时钟管理器)的结构和功能,详细分析了RS(Reed-Solomon)码编码器的工作过程,提出了一种连续RS编码器设计方案,给出了硬件电路和控制时序图。

This paper introduces the structure and functions of Virtex - II DCM module. The working process of RS encoder is analyzed. A design concept of continuous RS encoder is presented, and the design of control timing and circuits are provided.