Turbo码译码器VLSI结构的研究

Study on VLSI Architecture of Turbo decoder

探讨了Turbo码Log-MAP译码算法的VLSI实现技术。着重研究了计算状态度量的加比选结构以及实现MAP算法的滑窗法,并对整体译码方案进行了描述。还提出了可行的实现方案。通过实验仿真表明所用的方案能够达到精度要求。

This paper investigated the very large scale integrate circuit （VLSI） implementation of turbo decoder. The add- compare -select- offset ＂（ACSO） calculation unit that is used to calculate the state metrics was considered in detail. The slide - window technique was applied to the MAP decoding scheme. And a general architecture of turbo decoder was described. The simulation result shows that described scheme works well and can fulfill the requirements.