摘要
以10/100 Base-T以太网物理层的设计为基础,分别介绍了系统级芯片数字部分的硬件加速仿真,及借助FPGA实现数模混合验证的方法,并得出了两种验证方法的对比。最后,给出了10/100 Base-T以太网物理层芯片的流片结果。测试表明,整个系统的性能达到了设计要求。
Based on the physical layer design of 10/100 Base-T Ethernet, two verification methods, hardware accelerated emulation of the digital part on system level and mixed signal verification by FPGA, are described, and a comparison is made between the two methods. Finally, test results of the 10/]00 Base-T Ethernet physical layer chip is presented. According to the test, the performance of the whole system meets the specification.
出处
《微电子学》
CAS
CSCD
北大核心
2006年第2期136-140,144,共6页
Microelectronics
基金
上海市科委SDC项目(低功耗高速以太网物理层和模数转换芯核)资助(047062005)
