弹性分组环专用集成电路的可测性设计

Design for Testability of a Resilient Packet Ring ASIC

根据弹性分组环专用集成电路的具体情况,提出了相应的可测性设计(Design for Test-ability,DFT)方案,综合运用了三种DFT技术:扫描链、边界扫描测试和存储器内建自测试。介绍了三种技术的选取理由和原理,对其具体实现过程和结果进行了详细分析。DFT电路的实现大大降低了专用集成电路的测试难度,提高了故障覆盖率。

Based on the practical test requirements of resilient packet ring （RPR） ASIC,a design for Testability （DFT） strategy is presented, in which three different DFT methods are used. Principles and key methods used in the strategy are described, including scan chain, boundary scan test （B ST）, and memory built-in-sel-test （MBIST）. Implementation process and results of the DKF strategy are analyzed in detail. DFT circuits implemented in RPR ASIC reduces difficulties in circuit test and greatly improves fault coverage.