摘要
研究了信道纠错编码Turbo码,并提出了利用FPGA实现Turbo码编译码的方法。编码采用了顺序输入,并行编码,顺序输出。译码选用Max-Log-MAP算法,针对该算法采用查表法实现交织,以提高交织速度,译码器内部采用并行级联调用,以减小译码延时。通过计算机模拟仿真表明,所设计实现的Turbo码具有良好的性能和实用价值。
In this paper, a important channel error-correcting codes-Turbo codes had be research, a new implementation method of Turbo codes by FPGA was proposed. In order input use for coding , implement together coding and in order output. Max-Log-MAP algorithm be used for decoding,Be directed towards this algorithm, the way search for table be used for interleaver design, interleaver speed be improve, implement together in order link use in the decoding appliance for reduce in size delay of decoding. The simulation result testified that the whole system has good performance, and it can be put into practical use.
出处
《重庆邮电学院学报(自然科学版)》
2006年第2期187-191,共5页
Journal of Chongqing University of Posts and Telecommunications(Natural Sciences Edition)