基于记录缓冲的低功耗指令Cache方案

A Low-Power Instruction Cache Design Based on Record Buffer

现代微处理器大多采用片上Cache来缓解主存储器与中央处理器(CPU)之间速度的巨大差异,但Cache也成为处理器功耗的主要来源,尤其是其中大部分功耗来自于指令Cache.采用缓冲器可以过滤掉大部分的指令Cache访问,从而降低功耗,但仍存在相当程度不必要的存储体访问,据此提出了一种基于记录缓冲的低功耗指令Cache结构RBC.通过记录缓冲器和对存储体的改造,RBC能够过滤大部分不必要的存储体访问,有效地降低了Cache的功耗.对10个SPEC2000标准测试程序的仿真结果表明,与传统基于缓冲器的Cache结构相比,在仅牺牲6.01%处理器性能和3.75%面积的基础上,该方案可以节省24.33%的指令Cache功耗.

Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and central processing unit （CPU）, but these caches consume a significant fraction of total energy dissipation, especially the power dissipated by instruction cache itself is often a significant part of the power dissipated by the entire on-chip caches. Using buffer can filter most of instruction cache accesses and reduce it＇s power consumption, but there arestill many unnecessary data array accesses left, based on this idea. In this paper, a low-power instruction cache called RBC is proposed. With the record buffer and the modification on data array, RBC can filter most of the unnecessary cache activities, thus reducing energy consumption significantly. Experiments on 10 SPEC2000 benchmarks show that, compared with conventional block buffering cache, 24;33 % energy savings for instruction cache can be achieved, at the cost of only 6.01% slowdown and 3.75 % area overhead.