期刊文献+

同时多线程处理器上的动态分支预测器设计方案研究

Dynamic Branch Predictor Evaluation on Simultaneous Multithreading Processor
下载PDF
导出
摘要 同时多线程处理器(SMT)每个周期能够从多个线程中发射指令执行,从而大大地提高了超标量微处理器的指令吞吐量,但多个线程的同时执行也带来了许多硬件资源的共享冲突问题。其中,多个线程共享分支预测硬件的方案会对分支预测精度产生较大的影响。研究 SMT 处理器中分支处理方案对于处理器整体性能的影响,对于指导SMT 处理器的设计是十分重要的。本文利用 SMT 处理器模拟器,针对各线程运行独立应用的 SMT 结构实验评估了几种著名的分支预测方案;给出了在单线程和多线程情况下,分支预测方案对分支预测精度和处理器整体性能的影响的分析;总结出在这样的 SMT 结构中,各线程拥有独立的预测器是一种较好的选择,并且由于各独立预测器可以采用小而简单的结构,所以不会带来太多的硬件开销。 Simultaneous multithreading(SMT)can issue and exeeute multiple instructions from several independent thread each cycle. It greatly increases the throughput of the supersealar processors, but the simultaneous execution of multiple threads also brings some questions, such as the conflicts of hardware resource sharing. Sharing branch prediction hardware among multiple threads is one of the questions, this scheme may have great effect on branch prediction accuracy. It is very important to study the effect of branch resolving policies on the performance of SMT processors, because it can give us some advice on SMT processor design. By using SMT processor simulator, this paper tevaluated several famous branch prediction schemes on a SMT architecture that each thread executes independent applications, analyzed the effect of branch prediction schemes on branch prediction accuracy and overall performance of the processor on both single thread and multithread environment. We concluded that, on such a SMT processor, each thread having its own branch predictor is a good candidate, and because each predictor can be small and simple, it also adds little ad ditional hardware cost.
出处 《计算机科学》 CSCD 北大核心 2006年第3期239-243,274,共6页 Computer Science
基金 国家自然资助项目(60373043) 安徽省自然科学基金(050420206) 国家863高科技发展计划资助项目(2001AA111100)和(2002AA110010) 中国科学院知识创新工程重大项目(KGCX2-109)
关键词 同时多线程处理器 分支预测 硬件资源共享 硬件开销 SMT,Branch prediction, Hardware resource sharing, Hardware cost
  • 相关文献

参考文献12

  • 1Marr D T,Binns F,Hill D L,et al.Hyper-Threading Technology Architecture and Microarchitecture.Intel Technical Journal,2002,6(01).
  • 2Tullsen D,Eggers S,Emer J,et al.Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.In:Proc.23rd Annual Int ' l Symposium on Computer Architecture,1996.191 ~202.
  • 3Hily S,Seznec A.Branch Prediction and Simultaneous Multithreading.International Conference on Parallel Architecture and Compilation Techniques,1996.
  • 4Ramsay M,Feucht Ch,Lipasti M H.Exploring Efficient SMT Branch Predictor Design.University of Wisconsin-Madsin,Department of Electrical and Computer Engineering,2003.
  • 5Seznec A,Felix S,Krishnan V,et al.Design Tradeoffs for theAlpha EV8 Conditional Branch Predictor.Proceedings of the 29th Annual Symposium on Computer Architecture,May 25-29,2002.
  • 6Michaud P,Seznec A,Uhlig R.Trading conflict and capacity aliasing in conditional branch predictors.proceedings of the 24th annual International Symposium on Computer Architecture(ISCA-97),June 1997.
  • 7Lee J K F,Smith A J.Branch Prediction Strategies and Branch Target Buffer Design.IEEE Computer,1984,17 (1) :6~ 22.
  • 8Yen T Y,Patt Y N.Two-Level Adaptive Training Branch Prediction.In:Proceedings of the 24th Annual International Symposium on Microarchitecture,Nov 1991.51~61.
  • 9McFarling S.Combining branch predictors.[Technical Report TN-36].Digital Western Research Laboratory,June 1993.
  • 10Goncalves R,Ayguadé E,Valero M,et al.A Simulator for SMT Architectures:Evaluating Instruction Cache Topologies.Supported by the Spanish Ministry of Education(TIC98-511),2000.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部