基于CPLD控制的多路数据自动采集系统设计

A Design of Multiplex Data Auto Collecting System Based on CPLD

分析了常用模数转换器的控制时序,并以AD0809为例,对由CPLD构建的多路采集控制电路的内部原理做了详细分析。给出了基于CPLD控制的多路数据自动采集系统设计方案,仿真验证本方案是可行的。

Adopting CPLD, the design aims at producing a multiplex data collecting timing signal, and the collecting data will be saved into the cache memory. The CPU could read the up - to - the - minute result at any moment. This paper presents a common method of producing a multiplex data collecting timing signal with CPLD by taking AD0809 for example. Finally, this paper gives a detailed discussion on the operating circuit in CPLD.