DSP芯片中全加器电路的优化设计

A full-adder optimization design method in DSP

全加器在DSP芯片中是一个非常重要的逻辑器件,在DSP芯片内部存在着大量的加法器,通过对加法器的优化设计,可以使DSP芯片的性能得到提高。在本文中以CPL结构(Complementary passtransistor logic)加法器为基础提出了一种优化的加法器结构。并且通过HSPICE仿真,对28个晶体管的CMOS加法器、传统的CPL加法器和改进型的CPL加法器进行了比较。仿真的结果表明:改进型CPL加法器在功耗和延时等特性上比传统的28-TCMOS结构加法器和一般的CPL结构加法器有较大的提高。

Full adders are important components in the chip of digital signal processors （DSP）, and each chip comprises many full adder cells. So it is an effective method to enhance the DSP performance by improving the adder style. In this paper, a novel CPL style full adder is proposed. We have done HSPICE simulation runs of the new style adder, 28-T CMOS full adder and conventional CPL style full adder. The result shows that the novel CPL adder consumes less power and has higher speed compared with the previous two full adders.