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一种并行的Sticky位计算方法

A Parallel Method of Computing the Sticky Bits
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摘要 本文提出了通过基于预处理和逻辑转换的并行Sticky位的计算方法。该方法已经成功地应用到64位高性能CPU的浮点部件设计中,能有效提高浮点部件的延时性能。 The paper presents a parallel method of computing Sticky bits based upon preprocessing and logic conversion, which may improve the performance of floating point units and has been applied to the floating point units of high-performance 64-bit CPUs.
出处 《计算机工程与科学》 CSCD 2006年第4期124-125,129,共3页 Computer Engineering & Science
基金 国家自然科学基金资助项目(9020701
关键词 Sticky位 舍入 浮点加法 Sticky bit rounding floating-point addition
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参考文献4

  • 1ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating Point Arithmetic [S]. The Institute of Electrical and Electronics Engineers, 1985.
  • 2P K Montoye,E Hokenek,S L Runyon. Design of the IBM RISC System/6000 Floating-Point Execution Unit[J]. IBM Journal Research and Development, 1990, 34(1): 59-70.
  • 3M R Santoro. Design and Clocking of VLSI Multipliers[R]. Technical Report CSL-TR-89-397,Stanford University,1989.
  • 4M S Schmooker,K J Nowka. Leading Zero Anticipation and Detection:A Comparison of Methods[A]. Proc IEEE 15th Symp on Computer Arithmetic (ARITH15)[C].2001.7-12.

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