47Mb／s　RS码译码器的实现

Implementation of 47Mb/s RS Decoder

介绍了作者研制的用于数字磁记录器的（１２８，１１８）ＲＳ码和（１６２，１５４）ＲＳ码译码器的实现过程。该译码器采用ＢＭＬＦＳＲ－Ｃｈｉｅｎ－Ｆｏｒｎｅｙ译码算法并作了适当的修改。由于采用了流水线处理结构和可编程的逻辑器件以及某些关键环节上的优化设计，使得该译码器具有体积小、速度高等性能。

This paper describes the implementation fo (128, 118) RS decoder and (162, 154 )RS decoder which have been used in a digital tape recoder developped by us. Both of the decoders are based on BMLFSR-Chien-Forney algorithm. For pipepline structure and EPLD having found application as well as optimized design in some key steps having been used, the decoders have the property of small size and high processing speed.