多处理机并行处理模拟器的设计与实现

DESIGN AND IMPLEMENTATION OF MULTIPROCESSOR SIMULATOR FOR PARALLEL PROCESSING

“多处理机并行处理模拟器”是旨在帮助使用者巩固和加深对典型的并行计算机系统──ＭＩＭＤ多处理机系统──进行并行处理基本工作过程的理解，通过实际编写并行应用程序并对其模拟执行的过程进而引导其进行更为深入研究与开发的计算机辅助教学系统。通过对ＭＩＭＤ多处理机系统体系结构、编译器和操作系统基本特征的模拟，实现了对作业／作业步和ＤＯ循环级并行性的显式及隐式开发，依据“单独并行段”和“主动抽取”策略可对并行代码高效模拟执行。我们还将“回声”技术引入该模拟器，使其可自动检测系统的配置规模并准确定位连接故障。

The multiprocessor simulator for parallel processing is a computer-aided education system which aims at making users understand the working process of typical parallel computers-MIMD multiprocessor computer systems, setting up an environment in which they can design parallel applications and simtllate logical functions of the applications, and directing them to make a thorough reseach and development in the future. By simulating the main features of the architecture, compiler and operation system of MIMD multiprocessor computer systems, our simulator can develop the explicit and implicit concurrency in jobs/job steps and DO loops. According to the strategies single parallel segment and active extraction, it can execute parallel codes efficiently by simulation. Moreover, we introduce the echo method into our simulator, so that it is able to check the configuration of the system and locate connective defaults automatically.