期刊文献+

采用启发式方法放置去耦合电容的供电网络优化算法 被引量:1

Power Delivery Network Optimization with Decoupling Capacitor Allocation Based on Heuristic Method
下载PDF
导出
摘要 提出一种有效的启发式算法,利用芯片上的空白布局空间放置去耦合电容,实现供电网络的噪声优化,同时使去耦合电容占用较小的芯片面积资源·该算法采用伴随网络方法快速计算电路灵敏度,并应用等效电路技术来提高算法效率·实验结果表明,文中算法取得了很好的优化效果,并具有优化大规模电源/地线网络的能力· In this paper, an efficient heuristic method is presented to allocate decaps in the spare chip area based on power/ground network transient analysis in an area efficient way. This algorithm utilizes adjoint network method to efficiently calculate the sensitivity of objective function with respect to each decap values and uses equivalent circuit modeling technique to reduce the scale of the network which makes the whole optimization algorithm more efficient. Experimental results demonstrate that the algorithm is capable of optimizing very large scale power/ground networks.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2006年第4期513-518,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(60476014)
关键词 VLSI 电源/地线网络 噪声优化 去耦合电容 启发式方法 供电网络 VLSI power/ground network optimization decoupling capacitor heuristic method
  • 相关文献

参考文献9

  • 1Chen H H, Ling D D. Power supply noise analysis methodology for deep-submicron VLSI chip design[C]//Proceedings of the 34th ACM/IEEE Design Automation Conference, Anaheim, 1997: 638-643
  • 2Bai G, Bobba S, Hajj I N. Simulation and optimization of the power distribution network in VLSI circuits[C]//Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2000: 481-486
  • 3Tan X -D, Shi C -J. Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming[C]//Proceedings of the 36th ACM/IEEE Design Automation Conference, New Orleans, 1999: 78-83
  • 4Wu X -H, Hong X -L, Cai Y -C, et al. Area minimization of power distribution network using efficient nonlinear programming techniques[C]//Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2001: 153-157
  • 5Tan X -D, Shi C -J. Fast power-ground network optimization using equivalent circuit modeling[C]//Proceedings of the 38th ACM/IEEE Design Automation Conference, Las Vegas, 2001: 550-554
  • 6Zhao S -Y, Roy K K, Koh C -K. Decoupling capacitance allocation for power supply noise suppression[C]//Proceedings of IEEE/ACM International Symposium on Physical Design, Napa, 2001: 66-71
  • 7Su H -H, Roy K K, Sapatnekar S S, et al. An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts[C]//Proceedings of IEEE/ACM International Symposium on Physical Design, San Diego, 2002: 68-75
  • 8Fu Jingjing, Wu Xiaohai, Hong Xianlong, et al. An integrated tool for power/ground network design, optimization, and verification for cell based VLSIs[J]. Chinese Journal of Semiconductors, 2003, 24(3): 266-273
  • 9Chua L O, Lin P M. Computer-aided analysis of electronic circuits[M]. Englewood Cliffs: Prentice-Hall, Inc. 1975

同被引文献19

  • 1Lackey D E, Zuchowski P S, Bednar T R, et al. Managing power and performance for system-on-chip designs using voltage islands [C] //Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Los Alamitos: IEEE Computer Sodety Press, 2002:195-202.
  • 2Ma Q, Qian Z C, Young E F Y, et ul. MSV-driven floorplanning[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30 (8) : 1152-1162.
  • 3Zhou Q, Shi J, Liu B, et al. Floorplanning considering 1R drop in multiple supply voltages island designs [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(4): 638-646.
  • 4Leung M K Y, Chio E K I, Young E F Y. Postplacement voltage island generation [J].ACM Transactions on Design Automation of Electronic Systems, 2012, 17 ( 1 ) : Article No. 4.
  • 5Lee W P, Liu H Y, Chang Y W. An ILP algorithm for post- floorplanning voltage-island generation considering power- network planning [C] //Proceedings of the IEEE/ACM International Conference on Computer Aided Design. Los Alamitos: IEEE Computer Society Press, 2007:650-655.
  • 6Mak W K, Chen J W. Voltage island generation under performance requirement for SoC designs [C]//Proceedings of the Asia and South Pacific Design Automation Conference. Los Alamitos: IEEE Computer Soeiety Press, 2007:798-803.
  • 7Ma Q, Young E F Y. Multivoltage floorplan design [J]. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2010, 29(4); 607-617.
  • 8Lin J M, Hung Z X. SKB-tree: a fixed outline driven representation for modern floorplanning problems [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(3): 473-484.
  • 9Zhou P Q, Mishra V, Sapatnekar S S. Placement optimization of power supply pads based on locality [C] //Proceedings of the Design, Automation : Test in Europe Conference & Exhibition. Los Alamitos: IEEE Computer Society Press, 2013:1655-1660.
  • 10Yu T, Wong M D F. A novel and efficient method for power pad placement optimization [C] //Proceedings of the 14th International Symposium on Quality Electronic Design. Los Alamitos: IEEE Computer Society Press, 2013:158-163.

引证文献1

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部