基于FPGA的参数化时域脉冲压缩IP核的设计

Design of Parameterized IP Core for Time-Domain Pulse Compression Based on FPGA

数字脉冲压缩技术在现代雷达中已得到广泛应用,但不同雷达的参数各不相同,脉压处理电路也各不相同,因而使脉压电路的通用性甚差。该文介绍了一种基于现场可编程门阵列(FPGA)的参数化时域脉冲压缩IP核的设计方法。用该方法设计的脉冲压缩IP核通过参数化方式,使电路能适应脉冲压缩工作模式数、最大处理点数、输入数据率、数据/系数的宽度、乘法器流水级数及各种工作模式的对称性的改变,从而使脉压电路的通用性大为增强。

As well known, pulse compression is widely used to modern radars. For different radars, the parameters are different. It makes the pulse compression circuits be not universal. This paper introduces a method to design based on FPGA parameterized IP cores for time-domain pulse compression. In design of radar system, we can finish designing of the module for pulse compression with the IP core quickly.