一种2.4GHzCMOS低噪声放大器的优化设计

Optimization Design of A 2.4 GHz CMOS Low Noise Amplifier

通过对共源共栅结构的低噪声放大器的噪声和线性度的理论分析,得出该结构的放大器的噪声主要受第一级MOS管的影响,而线性度主要受第二级MOS管的影响。并由此提出一种对该电路的噪声和线性度的分别优化的方法。采用该方法设计一个基于TSMC0.25μmCMOS工艺、2.4GHz的低噪声放大器,仿真结果表明在2.4GHz下,它的噪声系数[NF]为1.15dB,增益S21为16.5dB,工作电压1.5V时,功耗为14mW,线性度IIP3为0.3dBm。

A detailed analysis of noise and linearity for the cascode architecture low noise amplifier （LNA）, which showed that the first MOSFET dominates the noise performance of the LNA and the second contributes more to the linearity, is present. So a compact strategy for CMOS （LNA） design, optimizing the noise performance and the linearity performance separately by designing the first and second MOSFET of the LNA, is obtained. A 2. 4 GHz LNA has been designed and simulated in a TSMC 0. 25μm CMOS technology to validate the proposed methodology. The LNA achieved 0. 3-dBm IIP3 with 16. 5-dB gain, 1.15 dB NF（noise figure） and9. 3 rnA@1. 5 V power comsumption.