一种并行解扰电路的VLSI实现

Parallel Descrambler Architecture

解扰电路是数字电视解扰系统的核心部分。着重介绍了实现并行解扰的电路原理图,从VLSI实现的角度来设计电路结构,给出仿真结果,采用0.35μm工艺实现。并行解扰电路集成在解调芯片中,在系统时钟28.8MHz控制下,正常工作,满足数字电视高速数据传输的要求。

An efficient method of parallel descrambler is proposed and especially it focuses on the circuit design in the VLSI implementation of the parallel descrambler. The circuit design is simulated. The final implementation using 0. 35μm library of CHARTER can work under control of the system clock of 28. 8 MHz. The parallel architecture is relatively simple, and can be realized in DSP.