基于修正ANT逻辑高速树形32 BitCarry Lookahead加法器

High-Speed 32-Bit Tree-Structured Carry Lookahead Adder Using Modified ANT Logic

一种用修正全NMOS管逻辑(ANT)实现的树形结构高速32bitcarryLookahead加法器,使用两相时钟动态CMOS逻辑、修正不反向ANT逻辑和二进制树形结构实现。该加法器运用0.25μm工艺,文中给出了修正ANT逻辑中所有晶体管的宽长尺寸和仿真结果,最高工作频率为2GHz,计算结果在3.5个时钟周期后有效。

This paper presents a high-speed 32-bit tree-structured carry-lookahead adder （CLA） using twophase clocking dynamic CMOS logic with modified noninverting all-n-transistor （ANT） blocks and binarytree structure. The adder is based on 0. 25μm CMOS technology, The size of each transistor and the wave of the simulation are also given. The highest operating clock frequency is up to 2. 0 GHz, while the output of the addition of two 32-bit binary numbers is completed in 3.5 cycles.