一种全搜索块匹配算法的FPGA实现及其应用

Implementation of a full search block matching algorithm using FPGA

研究一种全搜索块匹配的脉动阵列结构,将该结构的全搜索块匹配算法在赛林思V irtex-ⅡPro系列现场可编程逻辑门电路(简称FPGA)上综合并实现,给出在FPGA上实现该算法的面积使用和最高工作频率等结果.该结构可用于低码率的实时压缩应用,如MPEG-2.其最大特点在于可以在运动距离的最大值范围内任意设定运动距离P值,同时搜索区域可以是长宽任意值的区域.

A full search block matching algorithm of a systolic architecture was implemented in RTL level VHDL for low bit rate video compression applications. This implementation was synthesized for Xilinx FPGA family, Vitex2-Pro. The results of area occupation and maximum operating frequency are presented. This architecture is able to be applied in a real-time low bit rate application. Furthermore, there are three parameters in the implementation controlling the range of search area.