基于可重构S盒的常用分组密码算法的高速实现

High-speed Hardware Implementation of Common Block Cipher Algorithms Based on a Reconfigurable S-box

DES、3DES和AES是应用最广泛的分组密码算法,其可重构性和高速实现对可重构密码芯片的设计具有重要影响。该文分析了这3种算法的高速硬件实现,利用流水线、并行处理和重构的相关技术,提出了一种可重构S盒(RC-S)的结构,并在此基础上高速实现了DES、3DES和AES。基于RC-S实现的DES、3DES和AES吞吐率分别可达到7Gbps、2.3Gbps和1.4Gbps,工作时钟为110MHz。与其它同类设计相比,该文的设计在处理速度上有明显优势。

DES, 3DES and AES are the most widely used cipher algorithms, the reconfiguration and high-speed implementation of the three algorithms are important for the design of a reconfigurable cipher chip. In this paper, the high-speed hardware implementation of the three algorithms is analyzed, the structure of a reconfigurable S-box （RC-S） is proposed, and the high-speed implementation of DES, 3DES and AES based on RC-S, pipeline, parallel and reconfiguration are given. The throughput rate is 7Gbps tbr DES, 2.3Gbps lbr 3DES, 1.4Gbps tbr AES with a I IOMHz clock. A comparison is provided between the design and similar existing implementations, the comparison proves that the design can achieve performance better than other solutions.