Verilog到C翻译器的设计与实现

Design and Implementation of Verilog to C Translation Tool

介绍了一种将Verilog硬件描述转化到等价C/C++代码的自动翻译器的实现过程,并给出了简化Verilog行为模型的方法、非阻塞赋值串行化的优化算法和一些访存优化原则。该方法设计的翻译器的生成代码可直接由C/C++编译器汇编成可执行程序后进行仿真。采用龙芯RTL作为系统输入的测试表明,该方法的仿真速度可比一般仿真软件有成倍的增加,并能在系统评估和分析上发挥显著的成效。

A method of generating equivalent C/C＋＋ code from Verilog hardware descriptions is proposed in this paper. Besides, a way of simplifying behavioral model of Verilog and an optimization algorithm on nonblocking assignments are given. There are also some guidelines of memory arrangement. The generated code is then compiled by C/C＋＋ compiler to an executable program which can perform simulation directly. The test results based on Godson RTL code show that the simulation speed is much fast than that of common simulation software and this method does held a lot in performance evaluation and analysis.