DES算法FPGA实现的研究与比较

An Investigation into the FPGA Design of DES Encryption System

为满足无线网络通讯的数据安全要求,提出了用现场可编程门阵列(FPGA)实现DES加解密的方案,分别以减少器件面积和增加运算速度为目标来加以实现,并对这两种实现方法进行了比较。

Different ways of designing DES encryption system with Verilog HDL. One is the area optimized design and another is the performance optimized. Followed by a comparison of them.