摘要
为了在不降低快速响应热释电探测器响应速度的同时抑制器件的振动干扰,通过对快速响应热释电红外探测器的振动噪声机理和输出电信号的频谱分析,提出了数字降噪方案,并用基于FPGA的硬件电路来实现。文中还介绍了硬件的结构和FPGA代码实现,给出了降噪之后的实际效果。
In order to restrain the vibration noise while the reponse speed of fast-response pyroelectric detector is not depressed,the principles of vibration noise and the frequency spectrum of the output signal of fast-response pyroelectric detectors were analyzed.A digital method for noise restraining which is realized based on FPGA were presented. Hardware frames and the FPGA code were introduced.Finally, actual results after noise restraining were given.
出处
《红外与激光工程》
EI
CSCD
北大核心
2006年第2期201-203,共3页
Infrared and Laser Engineering
基金
云南省自然科学基金资助项目(2002F0022Q)
关键词
快速响应
热释电探测器
振动
降噪
数字化
Fast-response
Pyroelectric detector
Vibration
Noise restrain
Digitalization
