功率VDMOSFET结终端技术研究

Research on Junction Termination Design for Power VDMOSFETs

提出了一种多重场限环(FLR)终端结构的优化设计方法。这一方法给出了一种简单模拟结构用以绘制所谓的击穿电压-间距曲线,由这一曲线可以直接得到最优化结构,而不必进行试验也不易发生错误.由此种方法得到的结果与实验结果附合得非常好.我们在较大范围内对这一方法的适用性进行了研究,结果表明这一方法在中等电压范围FLR终端设计中非常有效.

A design methodology for the optimal multiple - field - limiting - ring（ FLR） termination structure is presented. In the methodology, a simple model structure is developed to find the so- called BV - spacing curve, from which the optimal structure can be obtained directly without trial and error. The results acquired by the methodology are in excellent agreement with the experimental results. The applicability of the methodology is also investigated in a wide scope, which shows that the methodology has a very good performance in the medium- voltage-range FLR termination design.