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基于DMA传输的并口设计实现 被引量:1

A High Speed Parallel Peripheral Interface Based on DMA Mode
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摘要 采用改进HARVARD总线结构的通用DSP中,一个可配置位宽的并口采用DMA(直接存储器存取)模式传输。该并口可以实现传输数据的打包解包和奇偶选择,同时支持ITU-R656视频标准的输入传输,对提高DSP的数据吞吐率发挥了重要的作用。 In a general purpose DSP which is based on modified Harvard architecture, a Parallel Peripheral Interface with a reconfigurable bitwidth is designed.The PPI is used with DSP's DMA engine.It allows data packing/unpacking to/from 16-bit words and ignores either the odd or the even elements in an input DataStream.Also itsupports three input modes for ITU-R 656-framed data.
出处 《科学技术与工程》 2006年第10期1407-1411,共5页 Science Technology and Engineering
基金 国家自然科学基金(60476013)资助
关键词 数字信号处理器(DSP) DMA 并口 ITU-R 656 异步时钟 DSP DMA parallel peripheral interface ITU-R 656 asynchronous clock
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  • 1[1]The ITU radiocommunication assembly,interfaces for digital component video signals in 525-line and 625-line television systems operating at the 4:2:2 level of recommendation ITU-R BT.601 (PART A).ITU -R Assembly,1998:2-4
  • 2[2]Lorenzen T.Interfacing micron MT9V022 image sensors to blackfin processors.Engineer-to-Engineer,2005 ;258(22):
  • 3[3]Stein M.Crossing the abyss:asynchronous signals in a synchronous world.Paradigm Works,2003; 24:
  • 4[4]Cummings C E.Synthesis and scripting techniques for designing multi-asynchronous clock designs.Sunburst Design,Inc,2001

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