接收器中并行数据与字节时钟同步的电路设计

Design of a Circuit Synchronizing the Byte Clock with the Parallel Data in the Deserializer

在串并转换接收器中,并行数据在字节时钟的作用下并行输出。如何保证同一时刻输出的并行数据属于同一个字节,即并行数据与字节时钟的同步,是串并转换接受器中的一个关键问题。根据串并转换电路可以使用移位寄存结构,字节时钟可以在串行时钟的基础上使用计数器得到,而计数器又模可变的特点,设计了一种在数据的串并转换中进行并行数据与字节时钟同步的电路,经过理论分析与软件仿真,证明电路性能良好可行。

In the deserializer, parallel data are clocked out by byte clock. It is of great importance to ensure that the output parallel data are in the same byte, or, the byte clock is synchronized with the parallel data. On the basis of the facts that the deserializer can be accomplished with shift register structure, byte clock can be attained by counting the bit clock, and a counter＇ s modulus can be variable, a circuit synchronizing the byte clock with the parallel data while the serial data are deserialized is designed. Theoretical analysis and software simulation show that this circuit has good performance.