10Gb/s CMOS宽带限幅放大器设计

Design of the 10Gb/s CMOS broadband limiting amplifier

作为光接收机前端的关键部分,限幅放大器要求具有高增益,足够带宽以及较宽的输入动态范围。本文在0.18μm CMOS工艺上设计了一种用于10Gb/s传输速率的限幅放大器。采用反比例级联结构和低电压降有源电感负载来提高系统带宽,达到了设计目标。仿真结果显示,该限幅放大器获得了约30dB的增益和10GHz的-3dB带宽,在10GHz范围内S11和S22都小于-10dB,电路功耗为100mW。

As the key component of optical receiver, design of a high - speed limiting amplifier with high gain, broadband and a wide dynamic input range is required. A limiting amplifier in 0. 18μm CMOS technology for 10Gb/s application is described. In this circuit, an inverse scahng technology is adopted and low voltage drop active inductor is used as active load to extend the bandwidth. Results from simulations show that the amplifier has achieved a -3dB bandwidth of 10GHz, a gain of 30dB, parameters Sll and S22 are better than - 10dB in the 10Ghz frequency range. The power consumption is 100mW.