改进的低功耗两步式ADC结构

A Modified Low- power Two-step ADC Archtechture

本文提出了一种改进的两步式ADC拓扑结构。当ADC的分辨率为n位时,这种结构只需要(2^(n/2+1-2))或(2^(n-1)/2+2^(n+1/2)-2)个比较器。与传统的两步式ADC相比,其比较器数目的大大减少,使得ADC电路的功耗和芯片面积随之显著降低。此结构适用于高速便携式VLSI系统。

A modified two-step ADC topology architecture is presented in this paper. It employs （2^n/2＋1-2）or（2^n-1/2）comparators when the ADC has n-bit resolution ,which is less than traditional two-step ADC. This architecture reduces the chip size and attains lower system power consumption and is applicable for high-speed portable equipment.