基于H.264滤波硬件结构的设计研究

Research on the Design of H.264 Deblocking Filter Hardware Structure

设计了一个有效的滤波器的硬件结构,使用具有可配置数据通道的8-bit移位寄存器来提供滤波器(并行输入,并行输出的FIR滤波器)所需要的水平和竖直方向上的数据,设计了两个SRAM片,一个用来存放当前图像数据,另一个用来存放相关联的数据。在0.25微米技术下的综合结果是:19.1K门(不包含和的两个SRAM),100MHz。

This paper offers an efficient hardware structure for deblocking filter. The horizontal and vertical data needed by the filter （parallel input and parallel output fir filter） is provided by a 8-bit shifting register which is configurable for data passage. It has two SRAMs, one for storing current picture data, the other is for storing correlative data. The comprehensive result under the circumstance of 0.25 micron is ：19.1k wire （the SRAM and the SRAM are not included）, 100 MHz.