一种新型混合模式BIST的低功耗设计

A New Low Power Design of Mixed-mode BIST

本文提出了一种基于折叠集的test-per-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计。该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的。

The mixed-mode BIST design is a effective method in built-in self-test. This paper gives a new low power optimization design for the mixed-mode BIST of test-per-clock structure based on folding set. In circuit structure, two-mode LFSR is applied for the organic combination of the two test generators.Different methods are used to optimize test generator of the pseudo random test sequences and that of folding test sequences in order to reduce the power consumption of the ciruit under test.