实时可重配置FFT处理器的ASIC设计

ASIC Design for Real-Time Reconfigurable FFT Processor

设计一种能够完成4,16,64,256或1 024点复数快速傅里叶变换(FFT)处理器芯片.16,64点运算采用基-4级联流水线结构,256,1 024点采用二维运算结构,数据采用块浮点表示.使用Synopsys公司的综合及布局布线工具在SMIC CMOS 0.18μm工艺上进行ASIC实现.该处理器芯片在100 MHz时钟频率连续工作时,处理一组1 024点FFT序列需要24.8μs,每隔10.24μs输出一组1 024点运算结果.该处理器芯片已应用于某宽带数字接收机中.

A complex data fast Fourier transforms （FFT） processor is proposed. This FFT processor can be reconfigured as a 4, 16, 64,256 or 1 024 points computation. Radix-4 pipelined architecture is adopted for 16 and 64 points computation. Two-dimensional architecture is adopted for 256 and 1 024 points computation. Block-floating point algorithm is adopt. The ASIC design is synthesized, placed and routed using Synopsys with SMIC CMOS 0.18 μm library. When the processor operates continuously at 100 MHz, it can calculate the first 1 024 complex points FFT in 24.8 μs, and then get 1 024 results in each 10.24 μs. The chip has been used in a kind of wide band digital receiver.