系统总线映射

System Bus Mapping

通讯作为新的基于平台设计的重要研究分支,其重要性越来越引起关注。在系统设计之后,需要对系统设计做功能映射与总线映射,本文从接口与桥电路延时对总线选择的影响进行研究,提出了考虑接口与桥电路延时的总线映射方法,并提出了多于两条总线的总线拓扑结构生成原则。最后给出了一个cplatform的总线映射实例。

With the increment of the abstract level of system description, system synthesis became more important than ever. As an important part of system synthesis, system bus mapping attracts more attention around the world. A novel method of system bus selection after system design was presented in this paper. Contrasted to other methods which focused on formal specification or two stage bus architecture or complicated trade-off between different bus selections, the proposed method emphasized the consideration about the affect of interface and bridge delay to reduce the re-mapping iterative times using the principle that the modules which have the approximate communication throughput can be hung on same bus. For System-on-a-Chip bus architecture is uncertain, it was also presented to generate the multi-stage bus architecture of the design using the principle that the closer buses have bigger throughputs between them. And the principles were implemented by simple matrix conversion. At last, an example which proved the method to be valid was demonstrated in this paper.