Q-Coder算术编码器的VHDL实现

VHDL implementation of the Q-Coder

现介绍了一种适合于硬件实现的二进制算术编码器Q-Coder,并使用VHDL语言实现了该算法。在Active-HDL软件中进行了功能仿真,并在QuartusⅡ软件中完成了综合以及后仿真。综合得到的最高时钟频率为36.3MHz。

A binary arithmetic coder named Q - Coder that is suit for being performed in hardware is introduced, which is also performed using VHDL. The pre - simulation is carried out with Active - HDL and synthesis and the post- simulation are conducted with Quartus Ⅱ . The estimated clock is 36.3MHz,