嵌入式实时系统容错集成技术的研究

Research on Fault Tolerance Integration Technology for Embedded Real-Time Systems

本文提出了一种用于嵌入式实时系统的集成检查点回卷、任务重复和 DVS 的容错方法。该方法支待处理器速度的在线调整,并根据系统的特点,分别插入额外的 SCP 或 CCP 点,有效使用检查点的存贮和比较功能,减少任务的执行时间,提高系统性能。通过概率原理导出了该方法任务的平均执行时间。仿真结果表明在 DMR 系统上,与原有的方法相比,所提出的方法明显减少了任务的平均执行时间。在此基础上,进一步提出了可适配处理器速度的算法,在减少任务执行时间的同时又节约系统能源。本文研究成果也可用于其它任务重复系统,如 TMR-F、DMR-F-1和 RFCS 等。

An integrated fault tolerance approach that provides checkpointing, task duplication and DVS （dynamic voltage scaling） for embedded systems is presented in this paper. This paper shows that, by supporting processors＇ speed adjustment during task execution and inserting additional StEPs or CCPs according to characteristics of systems, a sig nificant reduction in the execution time can be achieved. With SCPs and CCPs, we can use both the comparison and storage operations in an efficient way and improve the performance of checkpointing schemes. Average execution times to complete a task for the proposed approach are obtained, using the theory of probability. Simulation results show that compared to previous method, the proposed approach significantly reduces the task execution time of DMR checkpointL ing scheme. Furthermore, an adaptive processors＇ speed algorithm, combined with the dynamic voltage scaling scheme, is put forwarded to achieve power reduction. My research results may be applied to the other task duplication systems, such as TMR-F, DMR-F-1 and RFCS, etc.