低成本的两级扫描测试结构

A Two-Stage Scan Architecture for Cost-Effective Scan Testing

提出了一种两级扫描测试结构:根据电路结构信息对时序单元进行分组,同组的时序单元在测试生成电路中共享同一个伪输入;将时序单元划分到不同的时钟域,在测试向量的置入过程中只有很小一部分时序单元发生逻辑值的翻转;引入新的异或网络结构,消除了故障屏蔽效应.实验结果表明,该两级测试结构与以往的方法相比,在保证故障覆盖率的同时,大大降低了测试时间、测试功耗和测试数据量.

A two-stage scan architecture is proposed for cost-effective scan testing. Scan flipflops are grouped based on structural analysis, scan fllp-flops in the same group share the same pseudo primary input in the test generation circuit; scan flip-flops are divided into different clock domain, only a small number of them are activated when applying test vectors. A new XOR network architecture is proposed to compact test responses, which avoids any aliases. Experimental results show that test application time, test power as well as test data volume can be reduced using the new scan architecture without any degradation of fault coverage.