集成电路的设计验证

Design Verification of Integrated Circuit

集成电路设计业正面临着一系列的挑战:芯片性能越来越强,规模越来越大,开发周期越来越长,设计质量越来越难于控制。而随着半导体技术的发展,设计验证已经逐渐成为大规模集成电路设计的主要瓶颈。而设计验证最基本的内容是功能验证,用于判别设计规范和实现之间是否一致。对模拟验证、形式验证中的等价性检验和模型检验进行了介绍,然后引入传统方法的一种改进——基于覆盖率的验证方法。

IC design is facing a series of challenges, including stronger performance, larger scale and much longer design cycle. With the development of semiconductor technology, design verification is becoming the major bottle-neck of large scale integrated circuit design. And Functional Verification is the basic of design verification, which is used to validate whether the implementation accord with the specification, First, several approaches in design verification, such as simulated checking, equivalence checking and model checking are introduced. Then, base on the amelioration for conventional approaches in functional verification named coverage-driven approach is imported in the end.