基于VLIW体系结构的DSP寄存器堆的设计

Design of register file of DSP based on VLIW architecture

在研究了基于VLIW体系结构DSP的特点基础上,通过对寄存器堆的组织结构、组成单元、功能实现等方面的分析,提出了该结构寄存器堆的设计方案。该方案实现了多组数据的正确并行读写操作,满足了VLIW体系结构的CPU对多数据流处理的要求。该方案针对VLIW体系结构采用流水线操作、条件执行的特点,通过对写入数据分别采用写控制信号的方法,实现流水线阻塞和指令的条件执行。由于VLIW体系结构具有很多共性,该方案可以根据具体的硬件进行修改,具有很好的可移植性。

The DPS properties based on VLIW architecture are studied. A new design method of register file for VLIW architecture DSP is suggested through analyzing the structure, components and functions of the register file. The paralleled operation of reading and writing for data cluster is achieved. The writing control signals are used for the data input to realize the execution of pipeline blocking and order condition. This method can be modified according to different hardwares.