摘要
本文介绍了一种抖动抑制电路，可以对１～３次群ＨＤＢ３／ＡＭＩ码进行抖动抑制，并给出了实验结果。
A jitter restraining circuit which can restrain jittering in the HDB3/AMI code of 1st to 3rd groups is presented.And the experiment results are provided as well.
出处
《数字通信》
1996年第1期42-43,共2页
Digital Communications and Networks
关键词
锁相环
抖动抑制电路
数字网
jitter restraining,clock recovery,phase locked loop. clock without jitter
