维特比译码的双读出回溯算法及ASIC实现

The Double-readout Trace-back Algorithm for Viterbi Decoder and Its Complementation in ASIC

在分析维特比译码器回溯算法的基础上,归纳出回溯算法的规律,提出了双读出回溯(DRTB)算法。计算表明,DRTB算法在不增加硬件开销的情况下,使回溯运算速度达到原来的4倍。本文还介绍了基于DRTB算法幸存路径存储器单元(SMU)的ASIC结构和物理设计。对半导体集成电路的测试表明,本文提出的DRTB算法及电路结构是成功的。

A novel double-readout trace-back (DRTB) algorithm that used in Viter-bi Decoder for likelihood path series searching is developed by analyzing the rule oftrace-back operation.It increases the throughput rate up to 4 times without any ad-ditonal hardware overhead.The structural ASIC design of surviving path memoryunit (SMU) toward DRTB algorithm is described and it is applied in a Viterbi De-coder IC design.With being fabricated,the test results indicate that the DRTB al-gorithm and circuit design are successful as prediction.