以太网物理层中判决反馈均衡器VLSI优化设计

VLSI architecture optimization for DFE used in Ethernet

对以太网物理层中的判决反馈均衡器进行了VLSI优化设计,从硬件实现角度提出了两点改进措施,一是采用混合结构实现,二是系数调整单元复用。在0.18μm CMOS工艺下,改进后的判决反馈均衡器相比转置结构实现的判决反馈均衡器,速度提高16%,面积减少36%,功耗降低了39%。

An optimum design of Decision Feedback Equalizer （DFE） used in Ethernet was presented. Two improving measures for physical implementation-the hybrid structure and the share of coefficient adjusting unit were proposed. In 0.18μn CMOS process, the speed, area and power consumption of the improved DFE was optimized by 16%, 36% and 39% compared with the transposed structure implementation.