一种10位80 MS/s低功耗采样保持电路的设计

A 10-b 80 MS/s Low Power Sample-and-Hold Circuit

给出了一种基于开关电容(SC)电路的10位80 MHz采样频率低功耗采样保持电路。它是为一个10位80 MS/s流水线结构A/D转换器的前端采样模块设计的。在TSMC 0.25μmCMOS工艺,2.5 V电源电压下,该电路的采样频率为80 MHz;在奈奎斯特频率采样时,无杂散动态范围(SFDR)为75.4 dB,SNDR为71.8 dB,ENOB为11.6,输入信号范围可达160 MHz(两倍采样频率),此时SFDR仍大于70 dB。该电路功耗为16.8 mW。

A 10 b 80 MS/s low power sample-and-hold circuit based on switched-capacltor （SC） circuits was designed, which is intended for use in a 10-b 80 MS/s pipelined A/D converter. Simulated with 0. 25 μm CMOS process and 2.5 V supply power, the circuit achieves a sampling frequency of 80 MHz, and at Nyquist frequency, its SFDR and SNDR reaches 75.4 dB and 71.8 dB, respectively, with an input signal bandwidth up to 160 MHz. The circuit dissipates 16.8 mW of power.