一种基于新型寄存器结构的逐次逼近A/D转换器

A Successive Approximation Analog-to-Digital Converter Based on a New Register Architecture

介绍了一种10位CMOS逐次逼近型A／D转换器。在25kSPS采样频率以下，根据模拟输入端输入的0～10V模拟信号，通过逐次逼近逻辑，将其转化为10位无极性数字码。转换器的SAR寄存器结构采用了一种新的结构来实现D触发器。该转换器采用3μmCMOS工艺制作，信噪比为49dB，积分非线性为±0．5LSB。

A 10-bit CMOS successive approximation A/D converter is presented. With successive approximation logic, this A/D converter can convert 0 -10 V analog signals into 10-bit nonpolarity digital code at 25 kSPS sampling rate. And a novel structure is adopted for D-type flip-flop in successive approximation register （SAR）. Fabricated in 3 μm CMOS process, the A/D converter has a signal-to-noise ratio （SNR） of 49 dB, and an integral nonlinearity of ± 0.5 LSB.